Digital mean level detector

ABSTRACT

A digital mean level detector that processes the digital radar data so that the mean or RMS noise level is accurately determined and selected offset threshold levels can be varied to provide highly accurate and reliable signal detection. The system first provides mean level detection of the digital input signal which is applied to a threshold compare circuit having a plurality of thresholds such as two, for example. The output signals of the threshold compare circuit are encoded and sent both to a delay register and to an accumulator, with the outputs of both being applied to a subtractor for eliminating the oldest signal of a moving window sum held in the accumulator. The signal at the output of the subtractor is applied to the accumulator where it is added to the present signal at the output of the threshold compare circuit. At each range bin, the accumulated sum is then compared with an expected count representing the mean level of the noise for the selected number of range bins. The difference, representative of a predetermined error of the input noise level, is then adjusted and used to correct a signal detector having an offset threshold as determined by selected detection codes.

is [191 1 3,761,922 Evans 5] Sept. 25, 1973 DIGITAL MEAN LEVEL DETECTOR[57] ABSTRACT [75] inventor: Noml Evans San Pedro Cahf A digital meanlevel detector that processes the digital [73] Assignee: Hughes AircraftCompany, Culver radar data so that the mean or RMS noise level is accu-City, Calif. rately determined and selected offset threshold levels canbe varied to provide hi hly accurate and reliable [22] Flled: 1971signal detection. The system first provides mean level [21] Appl. No:188,435 detection of the digital input signal which is applied to athreshold compare circuit having a plurality of thresholds such as two,for example. The output signals [52]. Cl 343/5 343/7 343/l7'l R of thethreshold compare circuit are encoded and sent" [51] Int. Cl. GOls 7/34both to a delay register and to an accumulator, with the [58] Field ofSearch 343/5 DP, 17.1 R, Outputs of both being applied to a Subtractorfor elimi A nating the oldest signal of a moving window sum held in theaccumulator. The si nal at the output of the sub- [56] References Cltedtractor is applied to the ac cumulator where it is added UNITED STATESPATENTS to the present signal at the output of the threshold com-3,500,396 3/1970 Lampert et a1. 343/7 A pare circuit. At each range bin,the accumulated sum 3.617.998 11/1971 Freedman 343/7 A is then comparedwith an expected count representing 34871405 12H969 Molho 343/5 DP themean level of the noise for the selected number of 3'l49'333 Campbell343/l7'1 R range bins. The difference. representative of a prede- 3.63 lAnders et al. 4 r termined error of the input noise le el is thenadjusted and used to correct a signal detector having an offsetthreshold as determined by selected detection codes PrimaryExaminerBenjamin A. Borchelt Assistant Examiner-G. E. Montone Atwrney-W.H. MacAllister, Jr. et a1. 7 Claims 6 Drawing Figures Rcldur rJTrclnsmitter C C l C I 54 I Antenna l 25 l 32 45 48 1.. zfl COI'ITFO] Vm V T V V n A I ""7 I |4 RRcdpr A D Slgnol I gigs: l I Deluy I 20 I2eceiver Llmlter I M Threshold M Reglster 1 L l s b- 56 |6 23 F c soltractor 24 22 42 h i I I I i Accu- I mulctor I 26 I 51 3 Make? k' s'j LJ l j c c r ift-Tif l l a I l slgnol Subtrocior Threshold Dewy ICompurotor Set 72 7 C l '7 I I i I AConTrols 7 I w I S lgnul I*Processor 1 r 36 l l Dlspluy LO ffset D etechon J Parfienfled Sept. 25,1973 3,761,922

4 Sheets-Sheet r .L I 92 95 I I I Clock I I I04 I 12 Threshold 32 B|I B52 I r V smfr V 7' I 3 Register I A H d ngi BZIIS 94 Encoder I06 I S b II I U 23 Threshold I IracIor IBIO I 24 25 22 I V RegIsIer I I I i I16 Thh Id I res o 4 96 I 5 F I I L I I I Shjft I I Il/7 E B E'Ji'J H8 9 I22 IA I I 4 I I 2335 Adder \I Accumulator I a I I26 I F' T 62/{ I I In I I II A S e Add Detector ubIracIor w DIVICIB er rcompumtor To I I52IProcessor I I 60 I42 I 9 3 Threshold I c L I36 I 1 I46 I II M48 ISignal De lay I i I axis 320 3 Derecto r: r I 28 I Adder ComparaIor 10I62 1 Processor I72 I h h F g T res old /|66 I atented Sept. 25, 1973 4Sheets-Sheet ooN x o q DIGITAL MEAN LEVEL DETECTOR BACKGROUND OF THEINVENTION 1. Field of the Invention This invention relates to radardetection systems and more particularly to a digital mean level detectorthat accurately and reliably determines the input noise level andprovides a controlled offset threshold level for operation with desiredperformance characteristics.

2. Description of the Prior Art Conventionally for systems requiringsubstantially accurate detection of radar signals with desiredperformance characteristics such as with a constant false alarm rate,analog mean level detectors may be utilized such as described in US.Pat. No. 3,057,995 and digital mean level detectors may be utilized suchas those using conventional digital integrator or accumulatorarrangements. The analog mean level detector systems generally have anexponential weighting of the data over several adjacent range or dopplerbins which tends to substantially increase the measurement error. Adigital mean level detector constructed as an exact dual of the analogsystem would have the undesirable weighting characteristics of theanalog mean level detector. Also, in systems requiring digitaloperation, the analog system cannot be used without additional digitalto analog signal conversions The digital integrator approach has beenfound to be unable to measure the RMS (root mean square) noise level toa high degree of accuracy because of various problems associatedtherewith. In a digital integrator system, input noise quantized inamplitude to 8 bits, for example, at each range bin is applied to anaccumulator operating as a moving window to calculate the sum of aselected number of adjacent range bins. The accumulated sum thenrepresents the mean noise level of the input signal. A problemassociated with this type of detector is that a very large number ofbits are required to be processed through the moving window in order toobtain representative results. Also, the digital integrator allows largetargets to greatly desensitize the detector capability of the system,and further has the disadvantage that a larger sigma or measure of erroris provided at its output than is desirable, when occasional targets arepresent. It would be a substantial advantage to the art if a digitalmean level detector were provided that was substantially insensitive tohigh level signals such as target signals, and that allowed accuratedetermination of noise levels with a minimum number of samples.

SUMMARY OF THE INVENTION The digital mean level detector in accordancewith the principles of the invention receives the input signal which isquantized at each range bin, and then applies a signal to both athreshold comparator circuit and to a signal delay register. The inputsignal may be hard limited in some arrangements in accordance with theinvention. The threshold comparator circuit includes a plurality ofthreshold circuits each providing a signal which, after being passedthrough an encoder, is applied to a shift register having a storageequal to a predetermined number of range bins, forming a moving window.The output of the encoder is also applied through an adder circuit to anaccumulator which in turn applies an accumulated sum to a subtractorcircuit. The output of the subtractor circuit representing thedifference between the accumulated sum and the oldest bit in the shiftregister is also applied to the adder for being combined with the newestthreshold data. At each range bin, the accumulated sum is also sent to asubtractor and comparator circuit where it is subtracted from anexpected count value which may be 96 for the illustrated arrangement.The difference which relates to the decibels of error of the detectedmean level of the noise from the expected level is then appropriatelyscaled and applied to a signal detector circuit. The detector circuitwhich may include a plurality of detection thresholds for selection ofoffset levels having desired system performance characteristics, changesthe detection threshold as a function of the difference value so as tomaintain the selected performance characteristics. The detected signalis then sent to suitable utilization circuits. Thus the signal isrelatively insensitive to a large amplitude target signal both becauseof the hard limiting and because of the subtraction of the oldest bitfrom the accumulated moving window sum.

It is therefore an object of this invention to provide a simplified andhighly accurate mean level detector.

It is another object of this invention to provide a mean level detectorthat is relatively insensitive to large target signals or noiseexcursions.

It is another object of this invention to provide a mean level detectorsystem that provides selection of a desired system performancecharacteristic such as a constant false alarm rate without decreasingthe reliability of the detection.

It is still another object of this invention to provide a noisemeasuring detector that determines the mean noise level with a highdegree of accuracy.

It is another object of this invention to provide a mean level detectorin which various types of weightings can be implemented to providedesired performance characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS The novel features of this inventionas well as the invention itself, both as to its method of organizationand method of operation, will best be understood from the accompanyingdescription, taken in connection with the accompanying drawings, inwhich like reference characters refer to like parts, and in which:

FIG. 1 is a schematic block diagram showing the mean level detectorsystem in accordance with the invention;

FIG. 2 is a schematic block and circuit diagram showing the mean leveldetection system of FIG. I in further detail;

FIG. 3 is a graph of accumulated count versus input noise level in a 32range bin moving window for explaining the operation of the mean leveldetector in accordance with the invention;

FIG. 4 is a graph of probability of false alarm versus volts with theprobability of false alarm axis having a log distribution for explainingthe operation of the mean level detector for a Rayleigh distribution inaccordance with the principles of the invention;

FIG. 5 is a schematic diagram of experimental and calculated curves ofprobability of occurrence versus accumulated count in 32 range binsexplaining the operation of the invention; and

FIG. 6 is a schematic diagram of waveforms of amplitude versus time forfurther explaining the operation of the system of FIGS. 1 and 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIG. 1, themean level detector system may operate in a radar system which mayinclude a radar transmitter that applies pulses of energy through anantenna control unit 12 and through a suitable antenna 14 for radiationinto space. The return energy, reflected from targets (not shown), andincluding the target energy and noise energy is intercepted by theantenna 14 and applied through the antenna control unit 12 to a suitableradar receiver 16 responsive to a clock 18 which, for example, in theillustrated arrangement may define range bins 1 to m as shown in theradar beam or lobe 20 extending into space. The radar receiver 16 maydivide the signal into in-phase and quadrature signals to then berecombined at the output of either a digital MTI or a digital dopplerfilter bank of a doppler processor, which may provide a digital signalrepresenting the signal level in each range bin for application to asignal limiter 22. If the radar signal is in the analog form in thereceiver a suitable A to D converter 24 is provided at the output of theradar receiver 16, which signal, for example, may be an 8 bit signalrepresenting the signal amplitude in each range bin and which is appliedto the signal limiter 22. The 8 bit radar signal is also applied througha composite lead 26 to a signal delay circuit or unit 28 having a delayor digital storage selected equal to one-half of the width of the movingwindow. The signal limiter 22 may, for exam ple, pass only the two leastsignificant bits of the 8 bit number representing the signal amplitude,through a composite lead 32 to a detector unit 44 so as to provide theamplitude limiting. The signal passed by the limiter 22 is then appliedto a threshold compare circuit 42 of a mean level detection unit 44, andin turn after encoding in the circuit 42, through a composite lead 46 todelay register unit 48 as well as to an accumulator unit 50.

A subtractor 54 receives the oldest signal from the delay register unit48 and the accumulated sum from the accumulator 50 and develops adifference signal which is applied through a composite lead 56 to thesecond input of the accumulator 50. The accumulator mean level for theselected number of range bins for the moving window is then applied froma composite lead 51 to a subtractor and comparator circuit 60 of anoffset detection unit 62, which subtractor circuit subtracts theaccumulated mean level noise signal from an expected count. A thresholdset circuit 68 may be utilized to apply desired threshold levels to thesubtractor and comparator unit 60 for setting detection levels such as,for example, to provide a desired constant false alarm rate. The signalof a waveform 19 of amplitude versus time shows the incoming noisesignal with a target signal 23 at video frequency, for example. Thesignal ofa waveform 21 shows the mean level voltage provided by the meanlevel detection operation in accordance with the invention.

The threshold level provided by the subtractor and comparator circuit 60is then applied through a composite lead 72 to the detector 36 which mayinclude a plurality of detector circuits for providing detected signalsat a different or relative to different threshold levels. The output ofthe detector is then applied through a composite lead 78 to a suitablesignal processor 80 and in turn to suitable utilization units such as adisplay console 82 and a control unit 84. Thus the system of FIG. 1samples the signal, determines the mean level of the noise and utilizesthis determination to correct an offset detector.

Referring now to FIG. 2, which shows an illustrative example of a meandetector system in accordance with the invention in greater detail,signals from the radar receiver on the lead 23 may be applied throughthe A to D converter 24 (or received in digital form from the radarreceiver) to provide an 8 bit signal on the lead 25 which is applied tothe hard limiter 22 as well as to the signal delay circuit 28. The hardlimiter then passes a selected number of bits such as the two leastsignificant bits to the composite lead 32 and to n threshold circuits92, 94, 96 of the circuit 42, each respectively representing a differentthreshold level such as a digital value greater than 3 and greater than6 for the respective circuits 92 and 94. Each of the threshold circuits92, 94 and 96 may be a conventional digital compare circuit to provide asignal in response to an input signal com pared to a stored signal, asis well known in the art. Single binary bit signals provided by thethreshold circuits 92 and 94 are respectively applied to an encoderwhich in turn applies single bit signals to 32 bit shift registers 100and 102 through respective leads 104 and 106. A shift register 110,shown dotted, indicates that additional threshold levels withappropriate encoding may be utilized within the scope of the invention.The signals on the lead 104 and 106 are also applied through respectiveleads and 116 to a delay unit or register 1 17 to an adder 118 and inturn through a composite lead 120 to an accumulator 122, the compositelead 120, for example, transferring 8 binary bits. The accumulator 122may be any conventional memory storing an accumulated sum which isapplied through a composite lead 126 to a subtractor 128 which in turnalso receives the oldest bits from the shift registers 100 and 102. Thesubtractor 128 then develops a signal equal to the difference betweenthe oldest count and the accumulated count and applies a signal througha composite lead 56 and through the delay register 117 to a second inputof the adder 118. The accumulated signal on the composite lead 126 isalso applied to a subtractor 134 of the subtractor and comparatorcircuit 60 where it is subtracted from the count of 96 provided by aregister 136. The subtractor 134 provides the deviation from theexpected mean sum of 96, which signal is applied through a lead 138 to adivide by 8 circuit 40 to provide a scaled signal indicative of thenumber of decibels of deviation of the measured noise level. The scaledsignal is then applied from the circuit 140 through a lead 142 to anadder 144 and also receives a selected threshold value from a thresholdcircuit 146 as provided by selection switches 148. The adder 144corrects the threshold level during each range bin and applies thatdigital number through a composite lead 152 to the detector comparator154 to maintain a selected constant false alarm rate or any desiredperformance characteristic. The detected signal of the delayed or oldestdigital signal in the 16 clock delay shift register or delay circuit 28is then applied through a suitable lead to processor or otherutilization unit.

In order to provide the desired number of detector thresholds the unit62 may also include adder 162 and may include other adders such as 164,shown dotted, to indicate any desired number of thresholds that may beutilized within the principles of the invention. The

adder 162 receives the scaled signal from the lead 142 and a signal froma threshold circuit 166 in turn controlled by input switching circuit168 to apply a signal through a composite lead 170 to a detectorcomparator circuit 172, the output also being applied to the processors,for example.

Referring now to FIGS. 3 and 4, the operation of the detector systemwill be further explained. The input noise signal (receiver noise andother noise such as received noise) is assumed to be Rayleighdistributed as shown by a curve 180 of F1G.4 over the indicated voltagethreshold range. The detector of the invention determines the mean levelof the receiver noise for a Rayleigh probability distribution. The a-1r/2 is .the mean. value or level determined by the detector of theinvention based on a Rayleigh distribution. However, the invention isnot to be limited to a Rayleigh distribution but includes otherappropriate probability distributions. The Rayleigh distribution may bedefined as L/o' e L /2o' where L is the voltage level of the inputsignal. The weighting on the conditions of the threshold detector 42,using two levels T, and T are below the lowest threshold, above thefirst threshold T, but below the second T and above the highestthreshold T is selected by the following equations:

n W, P, W P W P where T, and T 100 and P, =1/6, P k and P, Thus n 1$W,+% W l/6 W =OandifW 1 then W, 3 and W 3. If all positive numbers areused for processing then W, 0, W 4, W, 6 and n W P, W P 3, which is theRMS noise level.

The following table shows the intermediate calculations and the movingwindow total over a 32 range bin sample and the mean level of 32 or 11,,3 X 32 96 is achieved, the count of 96 being the expected noise level.

TABLE I Input Noise Level Versus The Expected Level T, P, T, P, n, -6 db1.884 0.18 3.768 0.0007 24.03 -5 db 1.68 0.24 3.36 0.0038 30.93 4 db1.495 0.33 2.99 0.012 43.0 -3 db 1.33 0.42 2.66 0.032 58.15 -2 db 1.1850.5 2.37 0.064 68.0 1 db 1.055 0.58 2.110 0.112 81.5 0 db 0.94 0.65 1.880.18 96.0 +1 db 0.838 0.7 1.676 0.26 106.0 +2 db 0.745 0.75 1.490 0.34118.0 +3 db 0.665 0.79 1.330 0.42 128.0 +4 db 0.593 0.83 1.186 0.50138.0 +5 db 0.528 0.87 1.056 0.58 149.0 +6 db 0.47 0.9 0.94 0.66 158.0+7 db 0.42 0.92 0.84 0.7 162.0 +8 db 0.37 0.93 0.75 0.75 167.0

The above table is calculated from the equation:

1t is to be noted that the above table also shows the effect of changingthe input noise level in one db steps from the expected noise level toprovide n, which is the expected count if that noise level is selected.The above table for which the input noise level as expected is 0 db, hasan expected count of 96 as shown by a distribution curve 197 in FIG. 3for Table 1 data.

Referring also to FIG. 5, the results of a computer simulation for10,000 samples is shown by a curve 201 with the count plotted as afunction of probability of occurrence. This statistical type simulationwas for three discrete occurrence levels P (X) of H6, 2/6 and 3/6respectively having assigned weights W of 0, 4 and 6 and respectiveamplitudes of 2/6, 12/6 and 6/6. A curve 202 shows the calculated curvewhich corre sponds substantially with the experimental curve with theexpected count of 96.

The accuracy of determining the mean levels for the condition of FIG. 5may be estimated as follows:

where ,u. mean signal level, W the assigned weight, and P theprobability.

of 5 where 0', is the variance about the mean looking at one sampleevent.

where of is an average variance about the mean over 32 range bins, forexample. Thus the count of 96 has a l sigma uncertainty of plus or minus12.6 as an upper bound.

The second example of a processor in accordance with the invention withmore dynamic range has also been determined with W, O, W, 4 and W 8 asshown in the following table:

TABLE 11 Input Noise Level Versus The Expected Level V, P, V, P, n, 6 db1.88 0.18 4.7 10 23 -5 db 1.68 0.24 4.18 10" 31 4 db 1.495 0.33 3.72 1042.6 3 db 1.33 0.42 3.32 4X10 55 2 db 1.185 0.5 2.96 0.013 66 1 db 1.0550.58 2.64 0.032 79 0 db 0.94 0.66 2.35 0.065 94 1 db 0.838 0.7 2.09 0.122 db 0.745 0.75 1.86 0.185 3 db 0.665 0.79 1.66 0.26 134 4 db 0.593 0.831.48 0.34 5 db 0.528 0.87 1.32 0.46 168 6 db 0.47 0.9 1.175 0.52 182 7db 0.42 0.92 1.05 0.58 191 8 db 0.37 0.93 0.935 0.66 204 9 db 0.333 0.940.826 0.70 210 10 db 0.297 0.94 0.745 0.75 216 It is to be noted thatthe count for a normal noise level which is 94 in Table 11 is very closeto the mean level of 96. A curve 199 of FIG. 3 shows the relatively widerange of the Table I1 detector. It is to be understood that theprinciples of the invention include any suitable variations of thesystem design parameters such as the weighting parameters.

Referring now back to FIG. 2, the circuit operation of the digital meanlevel detector in accordance with the invention will be furtherexplained. The digital input signal which may be 8 bits, for example, issent to both the threshold compare circuit 42 as well as to the signaldelay register 28. 1f the signal exceeds the T threshold in thethreshold compare circuit 94 a 110 is generated, exceeds the lowerthreshold of the circuit 92 but not the threshold of the circuit 94, a100 is generated and if neither threshold is exceeded the output is 000.This three bit number or signal on the leads 104 and 106 is sent both tothe delay registers 48 and to the adder 118. Because the three weightednumbers 0, 4 and 6 are respectively represented by 000, 100 and 110,only two registers are required because a third register would containonly zeros. After a delay of 32 range bins, the signal in the registers48 is subtracted from the accumulated sum in the accumulator 122. Thedifference signal from the subtractor 128 is added to the incomingsignal in the adder 118 to provide the new sum for the sliding windowsubstantially at each clock pulse. As a result, the accumulator 122contains the sum of the weighted threshold crossings of 32 adjacent bitsof information and as a new bit comes into the accumulator the oldestbit is discarded giving the moving window effect.

It is to be noted that the mean noise level is determined so that anoffset threshold level can be accurately established. The determinationis made at a very low threshold level so that a large number ofcrossings are provided for rapid response and for accuracy. Thus themean level of the noise is determined with a large value for probabilityso that the number of samples may be relatively small for any desiredvalue.

At each range bin the accumulated sum is applied to the offset circuit62 and the subtractor 134 where the sum is subtracted from the expectedvalue of 96. A difference of 8 or may correspond approximately to a 1 dberror as read from the curves of FIG. 3 (or shown in Table I), whichdifference is divided by 8 (or by 10 if increased accuracy is desired)and then sent to the adder 144 of the detector circuit and to thedetector comparator circuit 154 as well as through adder 162 to detectorand comparator circuit 172. An example of the quantized signal levelsthat may be selected by the threshold circuits at the detector where theassociated codes and probability of false alarm (PFA) rates are listedbelow:

TABLE III db above Count Code PFA RMS noise 3 0011 0.37 0 4 0100 0.18+2.5 5 0101 0.067 +4.4 6 0110 0.018 +6. 7 0111 0.0045 +7.36 8 10000.0007 +8.5 9 1001 0.00013 +9.54 I0 1010 0.000014 +10.54

The threshold circuits 146 and 166 are shown with respective detectionthresholds code 0111 and code 1010. When the signal from the subtractorand comparator circuit 60 indicates an error of l or more db, the numberfrom this circuit is added to or subtracted from the selected detectioncode, depending on the polarity of the number provided by the dividecircuit 140. The codes may be selected with a separation of about 1 dbin the usable area so that a 1 db noise level change causes a 1 dbchange in the detection threshold. If more accurate control on the falsealarm rate is desired, more levels may be quantized into the noise sothat the separation between adjacent codes is smaller.

Referring now to FIG. 6 as well as to FIG. 2, the detection operationswill be explained in further detail in response to clock pulses ofawaveform 200. The pulses of the waveform 202 show the digital data atthe threshold compare circuit 42 from range bins l to 36. It is to benoted that the data of the waveform 202 may be received by the radarreceiver several clock periods earlier, depending on the type of radarutilized or the data may be radar data stored for subsequent processing.The pulses of a waveform 204 show the output of the shift registers ofthe delay unit 48 which is zero until the 33rd range bin data of thewaveform 202 is applied to the threshold unit 42. The subtractor outputsignal of the waveform 206 is zero until data is received at range binnumber 33 at which time the output is data from range bin 2 32, whichsubtracted output signal is applied to the adder 118 where the newestdata of range bin 33 is added thereto and stored in the accumulator asshown by a waveform 208. It is to be noted that the delay of delayregister 117 is provided at the adder 118 so that the contents of theaccumulator can be applied through the subtractor 128 prior to addingthe difference to the new input data. This pattern continues such as atrange bin 34, the register 48 outputs range bin 2 data to thesubtractor, the subtractor outputs being 3 33 data to the adder 118 andthe accumulator accumulates range bin data 3 to 34 after adding therange bin 34 data thereto. A waveform 210 shows the delayed data whichmay be 8 bits long, for example, at the output of the signal delaycircuit 28 which is the input signal to be detected after a delay of 16range bins so that detection occurs approximately at the center of themoving window. Thus in the illustrated arrangement, the moving windoweffect will have a width along the range sweep of 32 range bins but itis to be understood that any desired window length may be utilized. Atthe next range sweep or transmission of a pulse into space the sequenceas described is repeated similar to that explained.

Although the illustrated system is utilized to provide a constant falsealarm rate, the weightings may be varied to provide any desiredcharacteristic such as a linear response within the principles of theinvention. The system allows selection of thresholds at desired levelsand the assigning of any appropriate weights at each threshold.Different weightings require different expected counts and thresholdsettings as well as other appropriate system parameters. A significantfeature of the invention is that any desired weighting characteristicsmay be utilized.

Thus there has been described an improved detector that determines themean level with a high probability and then utilizes that determinationto control an offset detector so as to maintain a desired performancecharacteristic. When the mean level signal indicates an error of 1 ormore db, the number from this circuit is added or subtracted to selecteddetection codes. As a result, a selected false alarm rate or othersystem characteristic representative of a selected code is then reliablymaintained. By providing the codes with a separation of about 1 db inthe usable area, for example, a 1 db noise level change causes a 1 dbchange in the detection threshold. It is to be noted that the system isnot limited to any specific degree of accuracy but any desired number oflevels may be quantized into the noise so that the separation betweenadjacent codes is of a smaller amount.

What is claimed is:

1. A detector responsive to a radar signal comprising analog-to-digitalconverter means responsive to said radar signal to develop a digitalamplitude signal of a predetermined number of bits,

amplitude limiting means coupled to said analg-t0- digital convertermeans for passing a selected number of the least significant bits ofsaid digital amplitude signal,

threshold comparator means coupled to said amplitude limiting means andresponsive to said digital amplitude signal,

delay means responsive to said threshold comparator means,

accumulator means responsive to said threshold comparator means,

subtractor means responsive to said delay means and to said accumulatormeans, and coupled to an input of said accumulator means,

dividing means coupled to the output of said accumulator means toprovide a threshold error signal,

and detector comparator means coupled to said dividing means forreceiving said threshold error signal and responsive to said digitalamplitude signal for detecting the occurrences of the value of saiddigital signal exceeding a controlled threshold value with asubstantially constant false alarm rate.

2. The detector of claim l in which said accumulator means includes anadder for combining the output of said subtractor means and the outputof said threshold comparator means.

3. The combination of claim 2 in which said threshold comparator meansincludes n threshold circuits each having a threshold at a differentsignal level with each providing a single bit output signal.

4. The detector of claim 3 in which said dividing means includessubtractor means for subtracting an expected value from the output ofsaid subtractor means and includes a divider circuit responsive to saidsubtractor means for applying said threshold error signal to saiddetector comparator.

5. The detector of claim 4 in which said detector comparator meansincludes means for selecting detector thresholds and means for combiningthe selected threshold with said threshold error signal provided by saiddivider means.

6. A mean level detecting system for providing a substantially constantfalse alarm rate and being responsive to a digital radar signal having aselected plurality of bits during each of a plurality of clock intervalscomprising amplitude limiting means responsive to said digital radarsignal to pass a selected number of the least significant bits of saiddigital amplitude signal, threshold comparator means coupled to saidamplitude limiting means and responsive to the least sig nificant bitsof said digital amplitude signal and having a plurality of thresholdvalues for providing a threshold code signal representative of the valueof said digital radar signal, delay means responsive to said thresholdcomparator means and providing a delay equal to a selected number ofsaid clock intervals, accumulator means for accumulating a sum of thevalue of the signal provided by the threshold comparator means for apredetermined number of clock intervals, first subtractor means coupledto said delay means and to said accumulator means for subtracting theoldest data from said accumulated sum, first adder means coupled to saidaccumulator means and coupled to said threshold comparator means and tosaid subtractor means for combining the newest data with the output ofsaid first subtractor means, second subtractor means coupled to saidaccumulator means and including means for storing an expectedaccumulated sum for subtracting the accu mulated sum therefrom toprovide a difference sig nal, dividing means coupled to said secondsubtractor means for scaling said difference signal, second adder meanscoupled to said dividing means, threshold code selection means coupledto said second adder means, signal delay means responsive to saiddigital radar signal, and detector means coupled to said second addermeans and to said signal delay means for comparing the delayed digitalsignal with said threshold code after said code is combined with thescaled signal provided by said dividing means. 7. The combination ofclaim 6 in which said ampli tude limiting means passes two leastsignificant bits to provide hard limiting.

1. A detector responsive to a radar signal comprising analog-to-digitalconverter means responsive to said radar signal to develop a digitalamplitude signal of a predetermined number of bits, amplitude limitingmeans coupled to said analog-to-digital converter means for passing aselected number of the least significant bits of said digital amplitudesignal, threshold comparator means coupled to said amplitude limitingmeans and responsive to said digital amplitude signal, delay meansresponsive to said threshold comparator means, accumulator meansresponsive to said threshold comparator means, subtractor meansresponsive to said delay means and to said accumulator means, andcoupled to an input of said accumulator means, dividing means coupled tothe output of said accumulator means to provide a threshold errorsignal, and detector comparator means coupled to said dividing means forreceiving said threshold error signal and responsive to said digitalamplitude signal for detecting the occurrences of the value of saiddigital signal exceeding a controlled threshold value with asubstantially constant false alarm rate.
 2. The detector of claim 1 inwhich said accumulator means includes an adder for combining the outputof said subtractor means and the output of said threshold comparatormeans.
 3. The combination of claim 2 in which said threshold comparatormeans includes n threshold circuits each having a threshold at adifferent signal level with each providing a single bit output signal.4. The detector of claim 3 in which said dividing means includessubtractor means for subtracting an expected value from the output ofsaid subtractor means and includes a divider circuit responsive to saidsubtractor means for applying said threshold error signal to saiddetector comparator.
 5. The detector of claim 4 in which said detectorcomparator means includes means for selecting detector thresholds andmeans for combining the selected threshold with said threshold errorsignal provided by said divider means.
 6. A mean level detecting systemfor providing a substantially constant false alarm rate and beingresponsive to a digital radar signal having a selected plurality of bitsduring each of a plurality of clock intervals comprising amplitudelimiting means responsive to said digital radar signal to pass aselected number of the least significant bits of said digital amplitudesignal, threshold comparator means coupled to said amplitude limitingmeans and responsive to the least significant bits of said digitalamplitude signal and having a plurality of threshold values forproviding a threshold code signal representative of the value of saiddigital radar signal, delay means responsive to said thresholdcomparator means and providing a delay equal to a selected number ofsaid clock intervals, accumulator means for accumulating a sum of thevalue of the signal provided by the threshold comparator means for apredetermined number of clock intervals, first subtractor means coupledto said delay means and to said accumulator means for subtracting theoldest data from said accumulated sum, first adder means coupled to saidaccumulator means and coupled to said threshold comparator means and tosaid subtractor means for combining the newest data with the output ofsaid first subtractor means, second subtractor means coupled to saidaccumulator means and including means for storing an expectedaccumulated sum for subtracting the accumulated sum therefrom to providea difference signal, dividing means coupled to said second subtractormeans for scaling said difference signal, second adder means coupled tosaid dividing means, threshold code selection means coupled to saidsecond adder means, signal delay means responsive to said digital radarsignal, and detector means coupled to said second adder means and tosaid signal delay means for comparing the delayed digital signal withsaid threshold code after said code is combined with the scaled signalprovided by said dividing means.
 7. The combination of claim 6 in whichsaid amplitude limiting means passes two least significant bits toprovide hard limiting.